4c2af0e7baef22a45b0f5bb4315196e5.js 4.6 KB

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  1. ace.define("ace/mode/verilog_highlight_rules",["require","exports","module","ace/lib/oop","ace/mode/text_highlight_rules"], function(require, exports, module){"use strict";
  2. var oop = require("../lib/oop");
  3. var TextHighlightRules = require("./text_highlight_rules").TextHighlightRules;
  4. var VerilogHighlightRules = function () {
  5. var keywords = "always|and|assign|automatic|begin|buf|bufif0|bufif1|case|casex|casez|cell|cmos|config|" +
  6. "deassign|default|defparam|design|disable|edge|else|end|endcase|endconfig|endfunction|endgenerate|endmodule|" +
  7. "endprimitive|endspecify|endtable|endtask|event|for|force|forever|fork|function|generate|genvar|highz0|" +
  8. "highz1|if|ifnone|incdir|include|initial|inout|input|instance|integer|join|large|liblist|library|localparam|" +
  9. "macromodule|medium|module|nand|negedge|nmos|nor|noshowcancelled|not|notif0|notif1|or|output|parameter|pmos|" +
  10. "posedge|primitive|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|rcmos|real|realtime|" +
  11. "reg|release|repeat|rnmos|rpmos|rtran|rtranif0|rtranif1|scalared|showcancelled|signed|small|specify|specparam|" +
  12. "strong0|strong1|supply0|supply1|table|task|time|tran|tranif0|tranif1|tri|tri0|tri1|triand|trior|trireg|" +
  13. "unsigned|use|vectored|wait|wand|weak0|weak1|while|wire|wor|xnor|xor" +
  14. "begin|bufif0|bufif1|case|casex|casez|config|else|end|endcase|endconfig|endfunction|" +
  15. "endgenerate|endmodule|endprimitive|endspecify|endtable|endtask|for|forever|function|generate|if|ifnone|" +
  16. "macromodule|module|primitive|repeat|specify|table|task|while";
  17. var builtinConstants = ("true|false|null");
  18. var builtinFunctions = ("count|min|max|avg|sum|rank|now|coalesce|main");
  19. var keywordMapper = this.createKeywordMapper({
  20. "support.function": builtinFunctions,
  21. "keyword": keywords,
  22. "constant.language": builtinConstants
  23. }, "identifier", true);
  24. this.$rules = {
  25. "start": [{
  26. token: "comment",
  27. regex: "//.*$"
  28. }, {
  29. token: "comment.start",
  30. regex: "/\\*",
  31. next: [
  32. { token: "comment.end", regex: "\\*/", next: "start" },
  33. { defaultToken: "comment" }
  34. ]
  35. }, {
  36. token: "string.start",
  37. regex: '"',
  38. next: [
  39. { token: "constant.language.escape", regex: /\\(?:[ntvfa\\"]|[0-7]{1,3}|\x[a-fA-F\d]{1,2}|)/, consumeLineEnd: true },
  40. { token: "string.end", regex: '"|$', next: "start" },
  41. { defaultToken: "string" }
  42. ]
  43. }, {
  44. token: "string",
  45. regex: "'^[']'"
  46. }, {
  47. token: "constant.numeric",
  48. regex: "[+-]?\\d+(?:(?:\\.\\d*)?(?:[eE][+-]?\\d+)?)?\\b"
  49. }, {
  50. token: keywordMapper,
  51. regex: "[a-zA-Z_$][a-zA-Z0-9_$]*\\b"
  52. }, {
  53. token: "keyword.operator",
  54. regex: "\\+|\\-|\\/|\\/\\/|%|<@>|@>|<@|&|\\^|~|<|>|<=|=>|==|!=|<>|="
  55. }, {
  56. token: "paren.lparen",
  57. regex: "[\\(]"
  58. }, {
  59. token: "paren.rparen",
  60. regex: "[\\)]"
  61. }, {
  62. token: "text",
  63. regex: "\\s+"
  64. }]
  65. };
  66. this.normalizeRules();
  67. };
  68. oop.inherits(VerilogHighlightRules, TextHighlightRules);
  69. exports.VerilogHighlightRules = VerilogHighlightRules;
  70. });
  71. ace.define("ace/mode/verilog",["require","exports","module","ace/lib/oop","ace/mode/text","ace/mode/verilog_highlight_rules","ace/range"], function(require, exports, module){"use strict";
  72. var oop = require("../lib/oop");
  73. var TextMode = require("./text").Mode;
  74. var VerilogHighlightRules = require("./verilog_highlight_rules").VerilogHighlightRules;
  75. var Range = require("../range").Range;
  76. var Mode = function () {
  77. this.HighlightRules = VerilogHighlightRules;
  78. this.$behaviour = this.$defaultBehaviour;
  79. };
  80. oop.inherits(Mode, TextMode);
  81. (function () {
  82. this.lineCommentStart = "//";
  83. this.blockComment = { start: "/*", end: "*/" };
  84. this.$quotes = { '"': '"' };
  85. this.$id = "ace/mode/verilog";
  86. }).call(Mode.prototype);
  87. exports.Mode = Mode;
  88. }); (function() {
  89. ace.require(["ace/mode/verilog"], function(m) {
  90. if (typeof module == "object" && typeof exports == "object" && module) {
  91. module.exports = m;
  92. }
  93. });
  94. })();